Process technology scaling has helped in the realization of System on Chips (SoCs) that include many types of cores to implement complex functionalities.
According to the International Technology Roadmap for Semiconductor (ITRS), memory occupies an increasingly large portion of these SoCs and this trend is anticipated to continue. Various memory types such as SRAM, DRAM, and/or Flash memory have been embedded in SoCs. SRAM is a dominant embedded memory since it can be easily integrated with standard CMOS process technology.
Process technology scaling increases process variations due to random doping fluctuation, well proximity effect (WPE), and gate line edge roughness (LER). The process variations cause significant variations in circuit characteristics and make it difficult to model the behavior of the overall circuit. Therefore, due to the increased processing variation, estimating circuit performance is becoming very important at sub-100 nm process nodes. Excessively conservative design margins will increase complexity, design effort, and cost. On the other hand, underestimation of the process variation will lead to compromised performance or even functional failure.
Process variations can be generally divided into two categories: inter-die variation and intra-die variation. With the inter-die variation, the process parameters of all transistors in a die are shifted to one direction the same amount. The conventional design corner simulation methodology (i.e., slow, typical, and fast) can cover such a concurrent shift. On the other hand, the intra-die variation can cause process parameter shifts to vary in different directions for each transistor in a die, which results in process parameter mismatches between transistors. Thus, statistical simulation can be used to characterize the intra-die variation. The intra-die variation includes systematic variation and random variation. Threshold voltage (VT) mismatch due to random doping fluctuation is the significant source of the random variation. Since a limited number of dopant atoms are in the extremely small MOSFET channel area in nanoscaled process technology, the random doping fluctuation results in severe threshold variations which become a significant portion of the intra-die variations.
The threshold voltage mismatch is inversely proportional to the square root of the transistor area (width x length). Since memory cell size has been reduced with technology scaling to keep a high array efficiency, the threshold voltage mismatch has become a challenging issue in memory design. Memory failures according to the process variations can be generally categorized into 1) read stability failure, 2) write failure, 3) hold failure and 4) read access failure. The read stability failure and the hold failure can be considered to be due mainly to the threshold voltage mismatches between transistors in a memory cell. The write failure can be caused by the threshold voltage mismatch in a cell and a narrow wordline pulse width.
Variation in average bitcell read current (IAVG), variation in sense amplifier enable time (tSAE), and sense amplifier offset voltage (VOS—SA) are involved in the read access failure. A read access failure probability model is outlined in S. Mukhopadhyay, et al., “Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS”, IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 12, pp. 1859-1880, December 2005, which is incorporated herein in its entirety. The model proposed used a fixed VOS—SA, thereby ignoring the statistical distribution of VOS—SA. Additionally, variation in the tSAE was not considered. The distributions of tSAE and VOS—SA were described in R. Heald et al., “Variability in Sub-100 nm SRAM Designs”, IEEE/ACM Int. Con. on Computer Aided Design, pp. 347-352, Nov. 12, 2004, which is incorporated herein in its entirety. However, the statistical distributions of IAVG, tSAE, and VOS—SA have not been used in combination to optimize the memory architecture.
Sense amplifier optimization with the statistical simulation was emphasized to increase sensing margin by B. Amrutur et al., “A Replica Technique for Word Line and Sense Control in Low-Power SRAMs”, IEEE Journal of Solid State Circuits, vol. 33, no. 8, pp. 1208-1219, August 1998, which is incorporated herein by referenced in its entirety. The proper number of standard deviation of the threshold voltage mismatch according to the number of sense amplifiers was proposed to achieve high yield for sense amplifier in an article by S. Lovett et al., “Yield and Matching Implications for Static RAM Memory Array Sense-Amplifier Design”, IEEE Journal of Solid-State Circuits, vol. 35, no. 8, pp. 1200-1204, August 2000, which is incorporated herein by referenced in its entirety. The yield estimation model with the standard deviation of threshold voltage was presented in an article by T. Peng, “How much Mismatch Should be Simulated in the High Density SRAM Sense Amplifier Design”, IEEE Annual. Int. Reliability Physics Sym., pp. 672-673, April 2005, which is incorporated herein by referenced in its entirety.
Although individual aspects of process variation in memory design have been analyzed, the conventional methods fail to combine the variation in bitcell read current, the variation in the delay of the bitline tracking path which enables sense amplifier, and the sense amplifier offset voltage to achieve process variation tolerant memory designs and design methods for process variation tolerant memory designs